Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Phase Compensation Mode

The RX FIFO compensates for the phase difference between the read clock and write clocks. rx_clkout (RX parallel low-speed clock) clocks the write side of the RX FIFO. rx_coreclkin (FPGA fabric clock) or rx_clkout clocks the read side of the RX FIFO.

When phase compensation is used in double-width mode, the FPGA data width is doubled to allow the FPGA fabric clock to run at half rate, similar to the TX FIFO phase compensation in double-width mode.

Depth of RX FIFO is constant in this mode, therefore RX FIFO flag status can be ignored. You can tie tx_enh_data_valid with one.

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