Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

2.4.11. IP Core File Locations

When you generate your Transceiver Native PHY IP, the Quartus® Prime software generates the HDL files that define your instance of the IP. In addition, the Quartus Prime software generates an example Tcl script to compile and simulate your design in the ModelSim simulator. It also generates simulation scripts for Synopsys VCS, Aldec Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.

Figure 15. Directory Structure for Generated Files

The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.

Table 67.  Transceiver Native PHY Files and Directories
File Name Description
<project_dir> The top-level project directory.
<your_ip_name> .v or .vhd The top-level design file.
<your_ip_name> .qip A list of all files necessary for Quartus Prime compilation.
<your_ip_name> .bsf A Block Symbol File (.bsf) for your Transceiver Native PHY instance.
<project_dir>/<your_ip_name>/ The directory that stores the HDL files that define the Transceiver Native PHY IP.
<project_dir>/sim The simulation directory.
<project_dir>/sim/aldec Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys Simulation files for Synopsys simulation tools.
<project_dir>/synth The directory that stores files used for synthesis.

The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:

  • ModelSim SE
  • Synopsys VCS MX
  • Cadence NCSim

If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus Prime software is in VHDL. All the underlying files are written in Verilog or SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-language simulator.

For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus Prime Handbook.

The Transceiver Native PHY IP cores do not support the NativeLink feature in the Quartus Prime software.