Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.2.3. PLL Cascading as an Input Reference Clock Source

In this mode, the output of one PLL drives the reference clock input of another PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. In PLL cascading, PLL outputs are connected to the feedback and cascading clock network. The transceiver in Cyclone® 10 GX devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain.
  • To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
  • When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.