3.11. Using PLLs and Clock Networks
In Cyclone® 10 GX devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process. You can specify the channel configuration and PLL usage.
Did you find the information on this page useful?