Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Resetting the Transmitter During Device Operation

Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation. Use this reset sequence to reestablish a link or after dynamic reconfiguration. The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure.
  1. Perform the following steps:
    1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset while pll_cal_busy and tx_cal_busy are low.
    2. Deassert pll_powerdown after a minimum duration of 70 μs.
    3. Deassert tx_analogreset. This step can be done at the same time or after you deassert pll_powerdown.
  2. The pll_locked signal goes high after the TX PLL acquires lock. Wait for a minimum of 70 μs after deasserting tx_analogreset to monitor the pll_locked signal.
  3. Deassert tx_digitalreset, after pll_locked goes high. The tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset duration after tx_analogreset is deasserted.
    Note: You must reset the PCS blocks by asserting tx_digitalreset, every time you assert pll_powerdown and tx_analogreset.
Figure 149. Transmitter Reset Sequence During Device Operation