- 184.108.40.206. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 220.127.116.11. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 18.104.22.168. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants
10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Cyclone® 10 GX transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2.
The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) that interfaces with the Media Access Control (MAC), which has the optional Reconciliation Sub-layer (RS).
10GBASE-R is a single-channel protocol that runs independently. You can configure the transceivers to implement 10GBASE-R PHY functionality by using the presets of the Native PHY IP. The complete PCS and PHY solutions can be used to interface with a third-party PHY MAC layer as well.
The following 10GBASE-R variants area available from presets:
- 10GBASE-R Low Latency
- 10GBASE-R Register Mode
Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core.
10GBASE-R with IEEE 1588v2
When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and RX FIFO are set to register mode. The output clock frequency of tx_clkout and rx_clkout to the FPGA fabric is based on the PCS-PMA interface width. For example, if the PCS-PMA interface is 40-bit, tx_clkout and rx_clkout run at 10.3125 Gbps/40-bit = 257.8125 MHz.
The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data is running at 156.25 MHz interfacing with the MAC layer.
The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Cyclone® 10 GX transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as:
- Distributed systems in telecommunications
- Power generation and distribution
- Industrial automation
- Data acquisition
- Test equipment
The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.
The XGMII Clocking Scheme in 10GBASE-R
How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel Cyclone 10 GX Transceivers
Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with IEEE 1588v2
Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
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