Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL

Pin planner or Assignment Editor Name

Receiver High Data Rate Mode Equalizer AC Gain Control


Controls the AC gain of the continuous time linear equalizer (CTLE) in high data rate mode.

In high data rate mode, there is only one CTLE stage and 16 possible AC gain settings. Higher gain setting results in larger AC gain. The default value is set to RADP_CTLE_EQZ_1S_SEL_3 i.e. CTLE AC Gain Setting 3. This QSF assignment only takes effect when one stage CTLE is enabled. If configured in four stage mode, it has no effect on CTLE gain value.

Table 233.  Available Options



RADP_CTLE_EQZ_1S_SEL_<0 to 15>

CTLE AC Gain Setting < 0 to 15>

Assign To

RX serial data pin.


set_instance_assignment -name XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL <value> -to <rx_serial_data pin name>