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188.8.131.52. Implementing Multi-Channel x1 Non-Bonded Configuration
This configuration is an extension of the x1 non-bonded case. In the following example, 10 channels are connected to two instances of the PLL IP core. Two PLL instances are required because PLLs using the x1 clock network can only span the 6 channels within the same transceiver bank. A second PLL instance is required to provide the clock to the remaining 4 channels.
Because 10 channels are not bonded and are unrelated, you can use a different PLL type for the second PLL instance. It is also possible to use more than two PLL IP cores and have different PLLs driving different channels. If some channels are running at different data rates, then you need different PLLs driving different channels.
Steps to implement a Multi-Channel x1 Non-Bonded Configuration
- Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and instantiate the PLL IP core.
- Configure the PLL IP core using the IP Parameter Editor
- For the ATX PLL IP core do not include the Master CGB. If your design uses the ATX PLL IP core and more than 6 channels, the x1 Non-Bonded Configuration is not a suitable option. Multi-channel xN Non-Bonded or Multi-Channel x1/xN Non-Bonded are the required configurations when using the ATX PLL IP core and more than 6 channels in the Native PHY IP core.
- Refer to Figure 140 Implementing Multi-Channel xN Non-Bonded Configuration section or the Figure 141 Multi-Channel x1/xN Non-Bonded Example.
- For the fPLL IP core, set the PLL feedback operation mode to direct.
- For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
- Configure the Native PHY IP core using the IP Parameter Editor
- Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
- Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.
- Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
- The tx_serial_clk output port of the PLL IP core represents the high speed serial clock.
- The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.
- As shown in the figure above, connect the first 6 tx_serial_clk input to the first transceiver PLL instance.
- Connect the remaining 4 tx_serial_clk input to the second transceiver PLL instance.
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