Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

1.3. Calibration

Intel® Cyclone® 10 GX FPGAs contain a dedicated calibration engine to compensate for process variations. The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at optimum performance.

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance.

Note: For more information about CLKUSR electrical characteristics, refer to Intel® Cyclone® 10 GX Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For information about configuration requirements for the CLKUSR pin, refer to the Configuration, Design Security, and Remote System Upgrades in Intel® Cyclone® 10 GX Devices chapter in the Intel® Cyclone® 10 GX Core Fabric and General-Purpose I/O Handbook. For more information about calibration, refer to the Calibration chapter. For more information about CLKUSR pin requirements, refer to the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines.