Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

2.5.3. How to Implement Interlaken in Cyclone® 10 GX Transceivers

You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the Interlaken protocol PHY layer.

Cyclone® 10 GX devices provide three preset variations for Interlaken in the IP Parameter Editor:

  • Interlaken 1x6.25 Gbps
  • Interlaken 6x10.3 Gbps
  1. Instantiate the Cyclone® 10 GX Transceiver Native PHY IP from the IP Catalog (Installed IP > Library > Interface Protocols > Transceiver PHY > Cyclone® 10 GX Transceiver Native PHY).
    Refer to Select and Instantiate the PHY IP Core for more details.
  2. Select Interlaken from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
  3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Interlaken Transceiver Configuration Rules.... Or you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
  4. Click Generate to generate the Native PHY IP (this is your RTL file).
    Figure 27. Signals and Ports of Native PHY IP for Interlaken
  5. Configure and instantiate your PLL.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
  7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation.
  8. Connect the Native PHY IP to the PLL IP and the reset controller.
    Figure 28. Connection Guidelines for an Interlaken PHY Design

    This figure shows and example connection for an Interlake PHY design.

    For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic and RX deskew logic. The white blocks are your test logic or MAC layer logic.

  9. Simulate your design to verify its functionality.
    Figure 29.  12 Lanes Bonded Interlaken Link, TX Direction To show more details, three different time segments are shown with the same zoom level.
    Figure 30.  12 Lanes Bonded Interlaken Link, RX Direction To show more details, three different time segments are shown with different zoom level.