Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

6.2.1. Reading from the Reconfiguration Interface

Reading from the reconfiguration interface of the Transceiver Native PHY IP core or Transceiver PLL IP core retrieves the current value at a specific address. The dynamic reconfiguration interface is compliant to the AVMM specifications.
Figure 208. Reading from the Reconfiguration Interface

After the reconfig_read signal is asserted, the reconfig_waitrequest signal asserts for a few reconfig_clock cycles, then deasserts. This deassertion indicates the reconfig_readdata bus contains valid data.

Note: You must check for the internal configuration bus arbitration before performing reconfiguration. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.