Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 5/15/2020
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1. Intel® Cyclone® 10 GX Transceiver PHY Overview

Updated for:
Intel® Quartus® Prime Design Suite 20.1
This user guide provides details about the Intel® Cyclone® 10 GX transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. Intel® Quartus® Prime Pro Edition software version 17.1 supports the Intel® Cyclone® 10 GX transceiver PHY IP core. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.

Intel® ’s FPGA Intel® Cyclone® 10 GX devices offer up to 12 transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques.

The Intel® Cyclone® 10 GX devices have transceiver channels that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.

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