Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

1.4. Intel® Cyclone® 10 GX Transceiver PHY Overview Revision History

Document Version Changes
2017.12.28 Made the following changes:
  • Updated the " Intel® Cyclone® 10 GX Default Settings Preset" Figure.
  • Changed the transceiver count back to 6 for 10CX085 package F672 in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.
2017.11.06 Made the following changes:
  • Changed the description of the ATX PLL in the "Advanced Transmit (ATX) PLL" section.
  • Changed the transceiver counts for the F672 package in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.
  • Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section.
  • Changed the location of the PCIe Hard IP block in the " Cyclone® 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block" figure.
  • Changed the location of the PCIe Hard IP block in the " Cyclone® 10 GX Devices with 10 Transceiver Channels and One PCIe Hard IP Block" figure.
  • Changed the location of the PCIe Hard IP block in the " Cyclone® 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block" figure.
2017.05.08 Initial release.