Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Instantiating CMU PLL IP Core

The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
  1. Open the Quartus Prime software.
  2. Click Tools > IP Catalog.
  3. In IP Catalog, under Library > Interface Protocols > Transceiver PLL, select Transceiver CMU PLL Intel Arria 10/Cyclone 10 FPGA IP and click Add.
  4. In the New IP Variant dialog box, provide the IP instance name.
The CMU PLL IP core Parameter Editor window opens.