- 220.127.116.11. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 18.104.22.168. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 22.214.171.124. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
126.96.36.199. 8B/10B Encoder and Decoder
To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX 8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor. Platform Designer allows implementing the 8B/10B decoder in RX-only mode.
The following ports are added:
rx_datak and tx_datak indicate whether the parallel data is a control word or a data word. The incoming 8-bit data (tx_parallel_data) and the control identifier (tx_datak) are converted into a 10-bit data. After a power on reset, the 8B/10B encoder takes the 10-bit data from the RD- column. Next, the encoder chooses the 10-bit data from the RD+ column to maintain neutral disparity. The running disparity is shown by rx_runningdisp.
Did you find the information on this page useful?