- 22.214.171.124. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 126.96.36.199. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 188.8.131.52. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
7.4.1. Conditions That Require User Recalibration
Transceiver Reference Clock Availability and Stability After Device Power-Up
- During device power up, CLKUSR is asserted and running, but the transceiver reference clock remains deasserted until after the power up process is complete.
- During device power up, CLKUSR and the transceiver reference clock are asserted and running. When the device power up process is complete, the transceiver reference clock changes frequency. Either the transceiver reference clock could become unstable, or your application requires a different transceiver reference clock during normal operation, which could cause a data rate change.
After a Dynamic Reconfiguration Process That Triggers a Data Rate Change
After device power up in normal operation, you reconfigure the transceiver data rate by changing the channel configurations or the PLLs, recalibrate the:
- ATX PLL if ATX PLL has new VCO frequency to support new data rate.
- fPLL if the fPLL has new VCO frequency to support new data rate.
Note: fPLL recalibration is not needed if the dynamic reconfiguration method used to achieve new data rate (new VCO frequency) is done using the fPLL L counter /1,2,4,8 division factor.
- CDR/CMU as TX PLL. You must recalibrate the RX PMA followed by a TX PMA recalibration of the channel which uses the CMU as TX PLL.
- RX PMA and TX PMA channel if the transceiver configuration changes to support new data rates.
Other Conditions That Require User Recalibration
- Recalibrate the fPLL if the fPLL is connected as a second PLL (downstream cascaded PLL). The downstream fPLL received the reference clock from the upstream PLL (could be from fPLL/ CDR). Recalibrating the second fPLL is important especially if the upstream PLL output clock (which is the downstream fPLL's reference clock) is not present or stable during power-up calibration.
- For ATX PLL or fPLL used to drive PLL feedback compensation bonding, recalibrate the PLL after power up calibration.
You should avoid recalibrating the ATX PLL if another TX channel is in transmitting mode (clocked by another ATX PLL in the device). You need to do this to prevent a potential BER on neighboring RX channel placed next to a TX channel clocked by the ATX PLL. You can recalibrate the ATX PLL only if:
- The other TX channel that is in transmitting mode is clocked by fPLL or
- The other TX channel (clocked by another ATX PLL) must be placed under reset condition
If you are recalibrating your fPLL, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" section under PLLs and Clock Networks chapter.
You can initiate the recalibration process by writing to the specific recalibration registers. You must also reset the transceivers after performing user recalibration. For example, if you perform data rate auto-negotiation that involves PLL reconfiguration, and PLL and channel interface switching, then you must reset the transceivers.
The proper reset sequence is required after calibration. Intel recommends you use the Transceiver PHY Reset Controller IP which has tx_cal_busy and rx_cal_busy inputs and follow Intel's recommended reset sequence. You need to connect tx_cal_busy and rx_cal_busy from the Native PHY IP core outputs to the reset controller inputs in your design. Reset upon calibration is automatically processed when you perform user recalibration.
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