Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

1.2.1. Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes four or six transceiver channels in all devices.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

Figure 5. Transceiver Bank Architecture

Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.