Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Functional Description

The 1G/2.5G/5G/10G Multi-rate PHY Intel® FPGA IP core for Intel® Cyclone® 10 GX devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY).

Figure 55. Architecture of 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel® FPGA IP Parameter Editor.
The IP core includes the following interfaces:
  • Datapath client-interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
  • Management interface— Avalon® -MM host slave interface for PHY management.
  • Datapath Ethernet interface with the following available options:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link
  • Transceiver PHY dynamic reconfiguration interface—an Avalon® -MM interface to read and write the Intel® Cyclone® 10 GX Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds.
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following features:
  • USXGMII—10M/100M/1G/2.5G/5G/10G speeds
  • Full duplex data transmission
  • USXGMII Auto-Negotiation