Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

2.6.3.5.6. Transceiver Status and Reconfiguration Signals

Table 113.  Control and Status Signals
Signal Name Direction Width Description
rx_is_lockedtodata

Output

1

Asserted when the CDR is locked to the RX data.

tx_cal_busy

Output

1

Asserted when TX calibration is in progress.

rx_cal_busy

Output

1

Asserted when RX calibration is in progress.

Transceiver reconfiguration signals for Cyclone 10 GX devices
reconfig_clk Input 1

Reconfiguration signals connected to the reconfiguration block. The reconfig_clk signal provides the timing reference for this interface.

reconfig_reset Input 1
reconfig_address Input 10
reconfig_write Input 1
reconfig_read Input 1
reconfig_writedata Input 32
reconfig_readdata Output 32
reconfig_waitrequest Output 1