- 188.8.131.52. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 184.108.40.206. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 220.127.116.11. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
3. PLLs and Clock Networks
This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface.
As shown in the following figure, transceiver banks can have either four or six transceiver channels. For every three channels, you get one advanced transmit (ATX) PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB). Refer to the Device Transceiver Layout section to identify which devices have three channel transceiver banks.
The Cyclone 10 GX transceiver clocking architecture supports both bonded and non-bonded transceiver channel configurations. Channel bonding is used to minimize the clock skew between multiple transceiver channels. For Cyclone® 10 GX transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS bonding. Refer to the Channel Bonding section for more details.
Input Reference Clock Sources
Transmitter Clock Network
Clock Generation Block
FPGA Fabric-Transceiver Interface Clocking
Transmitter Data Path Interface Clocking
Receiver Data Path Interface Clocking
Unused/Idle Clock Line Requirements
PLL Feedback and Cascading Clock Network
Using PLLs and Clock Networks
PLLs and Clock Networks Revision History
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