Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3. PLLs and Clock Networks

This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface.

As shown in the following figure, transceiver banks can have either four or six transceiver channels. For every three channels, you get one advanced transmit (ATX) PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB). Refer to the Device Transceiver Layout section to identify which devices have three channel transceiver banks.

The Cyclone 10 GX transceiver clocking architecture supports both bonded and non-bonded transceiver channel configurations. Channel bonding is used to minimize the clock skew between multiple transceiver channels. For Cyclone® 10 GX transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS bonding. Refer to the Channel Bonding section for more details.

Figure 118.  Cyclone® 10 GX PLLs and Clock Networks