Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers

You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL architecture, and the reset controller before implementing the Basic (Enhanced PCS) Transceiver Configuration Rule.

  1. Open the IP Catalog and select the Cyclone® 10 GX Transceiver Native PHY IP.
    Refer to Select and Instantiate the PHY IP Core for more details.
  2. Select Basic (Enhanced PCS) from the Transceiver Configuration Rules list located under Datapath Options.
  3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Basic (Enhanced PCS) Transceiver Configuration Rules as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
  4. Click Finish to generate the Native PHY IP (this is your RTL file).
    Figure 77. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) Configurations
  5. Configure and instantiate the PLL.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
  7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
    Figure 78. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
  8. Simulate your design to verify its functionality.