Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.12. PLLs and Clock Networks Revision History

Document Version Changes
2023.04.14 In the PLLs section, added the following sub-sections:
  • Instantiating the ATX PLL IP Core
  • ATX PLL IP Core
  • Instantiating the fPLL IP Core
  • fPLL IP Core
  • Instantiating CMU PLL IP Core
  • CMU PLL IP Core
2019.05.13 Updated the Bonded Configurations topic.
2017.11.06 Made the following changes:
  • Added step 5 "If you reconfigure PLL for data rate change you must recalibrate the PLL" in Embedded Reconfiguration Streamer block of ATX PLL.
  • Added "The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not assert the analog reset signals indefinitely" in "Unused/Idle Clock Line Requirements" section.
  • Added a sentence in fPLL/CMU PLL "For protocol jitter compliance at datarate > 10 Gbps, Intel® recommends using the dedicated reference clock pin in the same triplet with the fPLL/CMU PLL as the input reference clock source."
2017.05.08 Initial release.