Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.8. Unused/Idle Clock Line Requirements

Unused or idle transceiver clock lines can degrade if the devices are powered up to normal operating conditions and the devices are not configured. This issue also affects designs that configure transceiver channels to use the idle clock lines at a later date by using dynamic reconfiguration or a new device programming file. Clock lines affected are unused idle receiver (RX) serial clock lines. Active RX serial clock lines and non-transceiver circuits are not impacted by this issue.

In order to prevent the performance degradation, configure the devices as long as it is powered up to normal operations. For idle transceiver RX channels, compile designs with the assignment described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not assert the analog reset signals indefinitely.