Visible to Intel only — GUID: yhl1505942471271
Ixiasoft
Visible to Intel only — GUID: yhl1505942471271
Ixiasoft
7.2.5.2. PMA Capability Registers for Calibration Status
Bit | Description |
---|---|
0x281[5] | PMA channel rx_cal_busy output enable. The power up default value is 0x1. 0x1: The rx_cal_busy output and 0x281[1] are asserted high whenever PMA TX or RX calibration is running. 0x0: The rx_cal_busy output or 0x281[1] is never asserted high. |
0x281[4] | PMA channel tx_cal_busy output enable. The power up default value is 0x1. 0x1: The tx_cal_busy output and 0x281[0] are asserted high whenever PMA TX or RX calibration is running. 0x0: The tx_cal_busy output or 0x281[0] is never asserted high. |
0x281[2] | PreSICE Avalon-MM interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. 0x1: PreSICE is controlling the internal configuration bus. 0x0: The user has control of the internal configuration bus. |
0x281[1] | PMA channel rx_cal_busy active high 0x1: PMA RX calibration is running 0x0: PMA RX calibration is done |
0x281[0] | PMA channel tx_cal_busy active high 0x1: PMA TX calibration is running 0x0: PMA TX calibration is done |
The PMA 0x281[5:4] is used to isolate the TX and RX calibration busy status. If you want rx_cal_busy unchanged during the TX calibration, you must set 0x281[5] to 0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX calibration. If you want tx_cal_busy unchanged during the RX calibration, you must set 0x281[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset due to the RX calibration. If you accidentally write 0x00 to 0x281[5:4], tx_cal_busy and rx_cal_busy is never activated to high in the user interface. Neither of the 0x281[1:0] registers go high either.
Bit | Description |
---|---|
0x280[2] | PreSICE Avalon-MM interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. 0x1: PreSICE is controlling the internal configuration bus. 0x0: The user has control of the internal configuration bus. |
0x280[1] | ATX PLL pll_cal_busy 0x1: ATX PLL calibration is running 0x0: ATX PLL calibration is done |
Bit | Description |
---|---|
0x280[2] | PreSICE Avalon-MM interface control 0x1: PreSICE is controlling the internal configuration bus. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. 0x0: The user has control of the internal configuration bus. |
0x280[1] | fPLL pll_cal_busy 0x1: fPLL calibration is running 0x0: fPLL calibration is done |
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