Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Enhanced PCS FIFO Operation

Phase Compensation Mode

Phase compensation mode ensures correct data transfer between the core clock and parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can tie tx_fifo_wr_en or rx_data_valid to 1.

Basic Mode

Basic mode allows you to drive the write and read side of a FIFO with different clock frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of the lane data rate divided by 66. The frequency range for tx_coreclkin or rx_coreclkin is (data rate/32) to (data rate/66). For best results, Intel recommends that tx_coreclkin or rx_coreclkin be set to (data rate/32). Monitor the FIFO flag to control write and read operations.

For TX FIFO, assert tx_enh_data_valid with the tx_fifo_pfull signal going low. This can be done with the following example assignment:

assign tx_enh_data_valid = ~tx_fifo_pfull;  
Figure 79. TX FIFO Basic Mode Operation

For RX FIFO, assert rx_enh_read_en with the rx_fifo_pempty signal going low. This can be done with the following example assignment:

assign rx_enh_read_en = ~rx_fifo_pempty;
Figure 80. RX FIFO Basic Mode Operation

If you are using even gear ratios, the rx_enh_data_valid signal is always high. For uneven gear ratios, rx_enh_data_valid toggles. RX parallel data is valid when rx_enh_data_valid is high. Discard invalid RX parallel data when the rx_enh_datavalid signal is low.

Register and Fast Register Mode

This FIFO mode is used for protocols, which require deterministic latency. You can tie tx_fifo_wr_en to 1.