- 220.127.116.11. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 18.104.22.168. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 22.214.171.124. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
3.5. FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of the previously mentioned clock networks. Instead, it chooses directly from the local routing between transceiver and FPGA fabric.
The transmitter channel forwards a parallel output clock tx_clkout to the FPGA fabric to clock the transmitter data and control signals. The receiver channel forwards a parallel output clock rx_clkout to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the receiver channel configuration, the parallel output clock is recovered from either the receiver serial data or the rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher).
The divided versions of the tx_clkout and rx_clkout are available as tx_pma_div_clkout and rx_pma_div_clkout, respectively.
The output frequency of tx_pma_div_clkout and rx_pma_div_clkout can be one of the following:
- A divided down version of the tx_clkout or rx_clkout respectively, where divide by 1 and divide by 2 ratios are available.
- A divided down version of the serializer clock where divide by 33, 40, and 66 ratios are available.
These clocks can be used to meet core timing by operating the TX and RX FIFO in double-width mode, as this halves the required clock frequency at the PCS to/from FPGA interface. These clocks can also be used to clock the core side of the TX and RX FIFOs when the Enhanced PCS Gearbox is used.
For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can use tx_pma_div_clkout with a divide-by-33 ratio to clock the write side of the TX FIFO, instead of using a PLL to generate the required clock frequency, or using an external clock source.
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