Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers

Table 219.   Avalon® Memory-Mapped Interface Arbitration Registers
Bit Offset Address Description
[0] 0x037 This bit arbitrates the control of Avalon® memory-mapped interface.
  • Set this bit to 0 to request control of the internal configuration bus by user.
  • Set this bit to 1 to pass the internal configuration bus control to PreSICE.
[1] 0x0 This bit indicates whether or not calibration is done. This is the inverted cal_busy signal. You can write to this bit; however, if you accidentally write 0x0 without enabling any calibration bit in 0x100, PreSICE may not set this bit to 0x1, and cal_busy remains high. Channel reset is triggered if cal_busy is connected to the reset controller.
When Read:
  • 1'b1: calibration done
  • 1'b0: calibration not done
When Write:
  • 1'b1: If user doesn't want to trigger calibration (with bit-0 1'b0 or 1'b1)
  • 1'b0: To trigger calibration (by also writing 1'b1 to bit-0)

The cal_busy signal is activated two clock cycles after you write 0x0 to this bit.

Note: During calibration when Nios® (PreSICE) is controlling the internal configuration bus, you can not read offset address 0x0. However, you can write 0x0 to offset address 0x0[0] to request bus access.
37 The transceiver channel, ATX PLL, and fPLL use the same offset address.