Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

6.2. Interacting with the Reconfiguration Interface

Each transceiver channel and PLL contains an Avalon Memory-Mapped (Avalon-MM) reconfiguration interface. The reconfiguration interface provides direct access to the programmable space of each channel and PLL. Communication with the channel and PLL reconfiguration interface requires an Avalon-MM master. Because each channel and PLL has its own dedicated Avalon-MM interface, you can dynamically modify channels either concurrently or sequentially, depending on how the Avalon-MM master is connected to the Avalon-MM reconfiguration interface.
Figure 206. Reconfiguration Interface in Cyclone® 10 GX Transceiver IP Cores

A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL instances, a Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across all channels to perform dynamic reconfiguration.

Avalon-MM masters interact with the reconfiguration interface by performing Avalon read and write operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write operations must comply with Avalon-MM specifications.

Figure 207. Top-Level Signals of the Reconfiguration Interface

The user-accessible Avalon-MM reconfiguration interface and PreSICE Avalon-MM interface share a single internal configuration bus. This bus is arbitrated to get access to the Avalon-MM interface of the channel or PLL. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.

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