Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents TX Bit Slip

To use the TX bit slip, select the Enable TX bitslip and Enable tx_std_bitslipboundarysel port options. This adds the tx_std_bitslipboundarysel input port. The TX PCS automatically slips the number of bits specified by tx_std_bitslipboundarysel. There is no port for TX bit slip. If there is more than one channel in the design, tx_std_bitslipboundarysel ports are multiplied by the number of channels. You can verify this feature by monitoring the tx_parallel_data port.

Enabling the TX bit slip feature is optional.

Note: The rx_parallel_data values in the following figures are based on the TX and RX bit reversal features being disabled.
Figure 106. TX Bit Slip in 8-bit Mode

tx_parallel_data = 8'hbc. tx_std_bitslipboundarysel = 5'b00001 (bit slip by 1 bit).

Figure 107. TX Bit Slip in 10-bit Mode

tx_parallel_data = 10'h3bc. tx_std_bitslipboundarysel = 5'b00011 (bit slip by 3 bits).

Figure 108. TX Bit Slip in 16-bit Mode

tx_parallel_data = 16'hfcbc. tx_std_bitslipboundarysel =5'b00011 (bit slip by 3 bits).

Figure 109. TX Bit Slip in 20-bit Mode tx_parallel_data = 20'hF3CBC. tx_std_bitslipboundarysel = 5'b00111 (bit slip by 7 bits).