Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.2.1. Dedicated Reference Clock Pins

To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL) can source the input reference clock directly from the reference clock buffer without passing through the reference clock network. The input reference clock is also fed into the reference clock network.

Figure 123. Dedicated Reference Clock PinsThere are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL and fPLL. The top refclk pin feeds the top ATX PLL and fPLL. The dedicated reference clock pins including the 4 channels bank can also drive the reference clock network.