Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks

Dynamic reconfiguration interfaces may need to be shared between multiple IP blocks to maximize transceiver channel utilization. The Native PHY provides the ability to create channels that are either simplex or duplex instances. However, each physical transceiver channel in Cyclone® 10 GX devices is fully duplex.

You can share the reconfiguration interfaces across different IP blocks by manually making a QSF assignment. There are two cases where a dynamic reconfiguration interface might need to be shared between multiple IP blocks:

  • Independent instances of simplex receivers and transmitters in the same physical location
  • Separate CMU PLL and TX channel in the same physical location

The following example shows one Native PHY IP instance of a TX-only channel and another instance of an RX-only channel.

Figure 217. Independent Instances of Simplex TX/RX in the Same Physical Location

The following example shows one Native PHY IP instance of a TX-only channel and an instance of a CMU PLL.

Figure 218. Separate CMU PLL and TX Channel in the Same Physical Location

Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores

To merge reconfiguration interfaces across multiple IP blocks, you must follow these rules:

  1. The control signals for the reconfiguration interfaces of the IP blocks must be driven by the same source. The reconfig_clk, reconfig_reset, reconfig_write, reconfig_read, reconfig_address, and reconfig_writedata ports of the two interfaces to be merged must be driven from the same source.
  2. You must make a QSF assignment to manually specify which two reconfiguration interfaces are to be merged.
    1. Use the XCVR_RECONFIG_GROUP assignment.
    2. Set the To field of the assignment to either the reconfiguration interfaces of the instances to be merged or to the pin names. The reconfiguration interface has the string twentynm_hssi_avmm_if_inst.
    3. Assign the two instances to be merged to the same reconfiguration group.

You cannot merge multiple reconfiguration interfaces when NPDME, optional reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native PHY IP core. 35

You cannot merge the TX and RX channels when the Shared reconfiguration interface parameter is enabled in the Native PHY IP core Parameter Editor. You can merge channels only if the reconfiguration interfaces are independent.

Refer to the following two examples to merge reconfiguration interfaces.

Using reconfiguration interface names

This example shows how to merge a transmit-only Native PHY instance with a receive-only instance using the reconfiguration interface names. These instances are assigned to reconfiguration group 0.

For Native PHY 0—transmit-only instance:

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst|<TX only instance name>*twentynm_hssi_avmm_if_inst*

For Native PHY 1—receive-only instance to be merged with Native PHY 0:

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst|<RX only instance name>*twentynm_hssi_avmm_if_inst*

Using pin names

This example shows how to merge a transmit-only Native PHY instance with a receive-only instance using pin names. These instances are assigned to reconfiguration group 1.

For Native PHY 0—transmit-only instance:

set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx[0]

For Native PHY 1—receive-only instance to be merged with Native PHY 0:

set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx[0]
35 The capability register is not available when merging a simplex Tx and a simplex Rx. Hence, the user cannot check the calibration status through capability register. Please refer to "Calibration" chapter on how to check the calibration status when merging a simplex Tx and simplex Rx.