Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.5. Inferring Multiplier, DSP, and Memory Functions from HDL Code

The Quartus® Prime Compiler automatically recognizes multipliers, multiply-accumulators, multiply-adders, or memory functions described in HDL code, and either converts the HDL code into respective IP core or maps them directly to device atoms or memory atoms. If the software converts the HDL code into an IP core, the software uses the Altera IP core code when you compile your design, even when you do not specifically instantiate the IP core. The software infers IP cores to take advantage of logic that you optimize for Altera devices. The area and performance of such logic can be better than the results from inferring generic logic from the same HDL code.

Additionally, you must use IP cores to access certain architecture-specific features, such as RAM, DSP blocks, and shift registers that provide improved performance compared with basic logic cells.

The Quartus® Prime software provides options to control the inference of certain types of IP cores.