Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

2.7. Including SDC Constraints from Lower-Level Partitions for
Third-Party IP Delivery

When exported partitions are compiled in a separate Intel® Quartus® Prime project, such as when a third-party designer is delivering IP, the project lead must transfer the top-level project framework information and constraints to the partitions, so that each designer has a consistent view of the constraints that apply to the entire design. If the independent partition designers make any changes or add any constraints, they might have to transfer new constraints back to the project lead, so that these constraints are included in final timing sign-off of the entire design. Many assignments from the partition are carried with the partition into the top-level design; however, SDC format constraints for the Timing Analyzer are not copied into the top-level design automatically.

Passing additional timing constraints from a partition to the top-level design must be managed carefully. You can design within a single Intel® Quartus® Prime project or a copy of the top-level design to simplify constraint management.

To ensure that there are no conflicts between the project lead’s top-level constraints and those added by the third-party IP designer, use two .sdc files for each separate Intel® Quartus® Prime project: an .sdc created by the project lead that includes project-wide constraints, and an .sdc created by the IP designer that includes partition-specific constraints.

The example design shown in the figure below is used to illustrate recommendations for managing the timing constraints in a third-party IP delivery flow. The top-level design instantiates a lower-level design block called module_A  that is set as a design partition and developed by an IP designer in a separate Intel® Quartus® Prime project.

Figure 29. Example Design to Illustrate SDC Constraints

In this top-level design, there is a single clock setting called clk associated with the FPGA input called top_level_clk. The top-level .sdc contains the following constraint for the clock:

create_clock -name {clk} -period 3.000 -waveform { 0.000 1.500 } \
[get_ports {TOP_LEVEL_CLK}]