- 184.108.40.206. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 220.127.116.11. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
2.4. Why Plan Partitions and Floorplan Assignments?
Planning involves setting up the design logic for partitioning and may also involve planning placement assignments to create a floorplan. Not all design flows require floorplan assignments. If you decide to add floorplan assignments later, when the design is close to completion, well-planned partitions make floorplan creation easier. Poor partition or floorplan assignments can worsen design area utilization and performance and make timing closure more difficult.
As FPGA devices get larger and more complex, following good design practices become more important for all design flows. Adhering to recommended synchronous design practices makes designs more robust and easier to debug. Using an incremental compilation flow adds additional steps and requirements to your project, but can provide significant benefits in design productivity by preserving the performance of critical blocks and reducing compilation time.
Partition Boundaries and Optimization
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