Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Specifying a Destination Library Name in a VHDL File

You can use the library synthesis directive to specify a library name in your VHDL source file. This directive takes the name of the destination library as a single string argument. Specify the library directive in a VHDL comment before the context clause for a primary design unit (that is, a package declaration, an entity declaration, or a configuration), with one of the supported keywords for synthesis directives, that is, altera, synthesis, pragma, synopsys, or exemplar.

The library directive overrides the default library destination work, the library setting specified for the current file in the Settings dialog box, any existing .qsf setting, any setting made through the Tcl interface, or any prior library directive in the current file. The directive remains effective until the end of the file or the next library synthesis directive.

The following example uses the library synthesis directive to create a library called my_lib containing the my_entity design unit:

-- synthesis library my_lib
library ieee;
use ieee.std_logic_1164.all;
entity my_entity(...)
end entity my_entity;
Note: You can specify a single destination library for all your design units in a given source file by specifying the library name in the Settings dialog box, editing the .qsf, or using the Tcl interface. To organize your design units in a single file into different libraries rather than just a single library, you can use the library directive to change the destination VHDL library in a source file.

The Intel® Quartus® Prime software generates an error if you use the library directive in a design unit.