Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

4.1.1. Running Rapid Recompile

During Rapid Recompile the Compiler reuses previous synthesis and fitting results whenever possible, and does not reprocess unchanged design blocks. Use Rapid Recompile to reduce timing variations and the total recompilation time after making small design changes.
Figure 36. Rapid Recompile

To run Rapid Recompile, follow these steps:

  1. Prior to initial compilation, click Assignments > Settings > Compiler Settings and turn on Enable Intermediate Fitter Snapshots. This option must be enabled to subsequently use the Rapid Recompile feature.
  2. To start Rapid Recompile following an initial compilation (or after running the Route stage of the Fitter), click Processing > Start > Start Rapid Recompile. Rapid Recompile implements the following types of design changes without full recompilation:
    • Changes to nodes tapped by the Signal Tap Logic Analyzer
    • Changes to combinational logic functions
    • Changes to state machine logic (for example, new states, state transition changes)
    • Changes to signal or bus latency or addition of pipeline registers
    • Changes to coefficients of an adder or multiplier
    • Changes register packing behavior of DSP, RAM, or I/O
    • Removal of unnecessary logic
    • Changes to synthesis directives

    The Incremental Compilation Preservation Summary report provides details about placement and routing implementation.

  3. Click the Rapid Recompile Preservation Summary report to view detailed information about the percentage of preserved compilation results.
    Figure 37. Rapid Recompile Preservation Summary