- 18.104.22.168. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 22.214.171.124. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
1.7.1. Preparing the Top-Level Design
In the top-level design, create project-wide settings, for example, device selection, global assignments for clocks and device I/O ports, and any global signal constraints to specify which signals can use global routing resources.
Next, create the appropriate design partition assignments and set the netlist type for each design partition that will be developed in a separate Intel® Quartus® Prime project to Empty. It may be necessary to constrain the location of partitions with LogicLock region assignments if they are timing-critical and are expected to change in future compilations, or if the designer or IP provider wants to place and route their design partition independently, to avoid location conflicts.
Finally, provide the top-level project framework to the partition designers, preferably through a source control system.
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