Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents State Machines

If your HDL code infers a state machine, the software maps the registers that represent the states into a new set of registers that implement the state machine. Most commonly, the software converts the state machine into a one-hot form in which one register represents each state. In this case, for Verilog HDL or VHDL designs, the registers take the name of the state register and the states.

For example, consider a Verilog HDL state machine in which the states are parameter state0 = 1, state1 = 2, state2 = 3, and in which the software declares the state machine register as reg [1:0] my_fsm. In this example, the three one-hot state registers are my_fsm.state0, my_fsm.state1, and my_fsm.state2.

An AHDL design explicitly specifies state machines with a state machine name. Your design names state machine registers with synthesized names based on the state machine name, but not the state names. For example, if a my_fsm state machine has four state bits, The software might synthesize these state bits with names such as my_fsm~12, my_fsm~13, my_fsm~14, and my_fsm~15.