Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Resolving Assignment Conflicts During Integration

When integrating lower-level design blocks, the project lead may notice some assignment conflicts. This can occur, for example, if the lower-level design block designers changed their LogicLock regions to account for additional logic or placement constraints, or if the designers applied I/O port timing constraints that differ from constraints added to the top-level design by the project lead. The project lead can address these conflicts by explicitly importing the partitions into the top‑level design, and using options in the Advanced Import Settings dialog box. After the project lead obtains the .qxp for each lower-level design block from the other designers, use the Import Design Partition command on the Project menu and specify the partition in the top-level design that is represented by the lower-level design block .qxp. Repeat this import process for each partition in the design. After you have imported each partition once, you can select all the design partitions and use the Reimport using latest import files at previous locations option to import all the files from their previous locations at one time. To address assignment conflicts, the project lead can take one or both of the following actions:
  • Allow new assignments to be imported
  • Allow existing assignments to be replaced or updated

When LogicLock region assignment conflicts occur, the project lead may take one of the following actions:

  • Allow the imported region to replace the existing region
  • Allow the imported region to update the existing region
  • Skip assignment import for regions with conflicts

If the placement of different lower-level design blocks conflict, the project lead can also set the set the partition’s Fitter Preservation Level to Netlist Only, which allows the software to re-perform placement and routing with the imported netlist.