Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.14. Power-Up Don’t Care

This logic option allows the Compiler to optimize registers in your design that do not have a defined power-up condition.

For example, your design might have a register with its D input tied to VCC, and with no clear signal or other secondary signals. If you turn on this option, the Compiler can choose for the register to power up to VCC. Therefore, the output of the register is always VCC. The Compiler can remove the register and connect its output to VCC. If you turn this option off or if you set a Power-Up Level assignment of Low for this register, the register transitions from GND to VCC when your design starts up on the first clock signal. Thus, the register is at VCC and you cannot remove the register. Similarly, if the register has a clear signal, the Compiler cannot remove the register because after asserting the clear signal, the register transitions again to GND and back to VCC.

If the Compiler performs a Power-Up Don’t Care optimization that allows it to remove a register, it issues a message to indicate that it is doing so.

This project-wide option does not apply to registers that have the Power-Up Level logic option set to either High or Low.