ID 683283
Date 9/24/2018
Public

## 3.5.11. Full Case Attribute

A Verilog HDL case statement is full when its case items cover all possible binary values of the case expression or when a default case statement is present. A full_case attribute attached to a case statement header that is not full forces synthesis to treat the unspecified states as a don’t care value. VHDL case statements must be full, so the attribute does not apply to VHDL.

Using this attribute on a case statement that is not full allows you to avoid the latch inference problems.

Note: Latches have limited support in formal verification tools. Do not infer latches unintentionally, for example, through an incomplete case statement when using formal verification.

Formal verification tools support the full_case synthesis attribute (with limited support for attribute syntax, as described in Synthesis Attributes).

Using the full_case attribute might cause a simulation mismatch between the Verilog HDL functional and the post- Intel® Quartus® Prime simulation because unknown case statement cases can still function as latches during functional simulation. For example, a simulation mismatch can occur with the code in Table 49 when sel is 2'b11 because a functional HDL simulation output behaves as a latch and the Intel® Quartus® Prime simulation output behaves as a don’t care value.

Note: Altera recommends making the case statement “full” in your regular HDL code, instead of using the full_case attribute.
Table 49.   A full_case AttributeThe case statement in this example is not full because you do not specify some sel binary values. Because you use the full_case attribute, synthesis treats the output as “don’t care” when the sel input is 2'b11.
HDL Code
Verilog HDL
module full_case (a, sel, y);
input [3:0] a;
input [1:0] sel;
output y;
reg y;
always @ (a or sel)
case (sel) 			// synthesis full_case
2'b00: y=a[0];
2'b01: y=a[1];
2'b10: y=a[2];
endcase  endmodule

Verilog-2001 syntax also accepts the statements in Table 50 in the case header instead of the comment form as shown in Table 49.

Table 50.  Syntax for the full_case Attribute
HDL Syntax
Verilog-2001
(* full_case *) case (sel)