- 22.214.171.124. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
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3.5.11. Full Case Attribute
A Verilog HDL case statement is full when its case items cover all possible binary values of the case expression or when a default case statement is present. A full_case attribute attached to a case statement header that is not full forces synthesis to treat the unspecified states as a don’t care value. VHDL case statements must be full, so the attribute does not apply to VHDL.
Using this attribute on a case statement that is not full allows you to avoid the latch inference problems.
Formal verification tools support the full_case synthesis attribute (with limited support for attribute syntax, as described in Synthesis Attributes).
Using the full_case attribute might cause a simulation mismatch between the Verilog HDL functional and the post- Intel® Quartus® Prime simulation because unknown case statement cases can still function as latches during functional simulation. For example, a simulation mismatch can occur with the code in Table 49 when sel is 2'b11 because a functional HDL simulation output behaves as a latch and the Intel® Quartus® Prime simulation output behaves as a don’t care value.
Verilog-2001 syntax also accepts the statements in Table 50 in the case header instead of the comment form as shown in Table 49.
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