ID 683283
Date 9/24/2018
Public

## 3.2.1.1.2. Hierarchical Design Configurations

A design can have more than one configuration. For example, you can define a configuration that specifies the source code you use in particular instances in a sub-hierarchy, and then define a configuration for a higher level of the design.

For example, suppose a subhierarchy of a design is an eight-bit adder, and the RTL Verilog code describes the adder in a logical library named rtllib. The gate-level code describes the adder in the gatelib logical library. If you want to use the gate-level code for the 0 (zero) bit of the adder and the RTL level code for the other seven bits, the configuration might appear as follows:

### Gate-level code for the 0 (zero) bit of the adder

config cfg1;
default liblist rtllib;
endconfig

If you are instantiating this eight-bit adder eight times to create a 64-bit adder, use configuration cfg1 for the first instance of the eight-bit adder, but not in any other instance. A configuration that performs this function is shown below:

### Use configuration cfg1 for first instance of eight-bit adder

config cfg2;
endconfig