Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Example 2—Input Register in Partition Fed by an Inverted Input Pin or Output Register in Partition Feeding an Inverted Output Pin

In this example, a subdesign designated as a separate partition contains a register. The top-level design in the figure instantiates the subdesign as an input register with the input pin inverted. The top-level design instantiates the subdesign as an output register with the signal inverted before feeding an output pin.
Figure 20. Top-Level Design Instantiating Subdesign as an Input Register with an Inverted Input Pin

Figure 21. Top-Level Design Instantiating the Subdesign as an Output Register Feeding an Inverted Output Pin

In these cases, the Quartus® Prime software does not perform register packing. If there is a Fast Input Register assignment on pin in, as shown in the top figure, or a Fast Output Register assignment on pin out, as shown in the bottom figure, the Quartus® Prime software issues a warning that the Fitter cannot pack the node to an I/O pin because the node and I/O cell are connected across a design partition boundary.

This type of register packing is not allowed because it requires moving logic across a design partition boundary to place into a single I/O device atom. To perform register packing, either the register must be moved out of the subdesign partition, or the inverter must be moved into the subdesign partition to be implemented in the register.

To allow the Quartus® Prime software to pack the single register in the subdesign with the input pin in, as shown in top figure or the output pin out, as shown in the bottom figure, restructure your HDL code to place the register in the same partition as the inverter by making one of the following changes:

  • Move the register from the subdesign partition into the top-level partition containing the pin. Doing so ensures that the Fitter can optimize the I/O register and inverter without violating partition boundaries.
  • Move the inverter from the top-level block into the subdesign, and then connect the subdesign directly to a pin in the top-level design. Doing so allows the Fitter to optimize the inverter into the register implementation, so that the register is directly connected to a pin, which enables register packing.