Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Example Step 1—Project Lead Produces .sdc with Project-Wide Constraints for Lower-Level Partitions

The device input top_level_clk in Figure 29 drives the input_clk port of module_A. To make sure the clock constraint is passed correctly to the partition, the project lead creates an .sdc with project-wide constraints for module_A that contains the following command:

create_clock -name {clk} -period 3.000 -waveform { 0.000 1.500 } [get_ports {INPUT_CLK}]

The designer of module_A includes this .sdc as part of the separate Intel® Quartus® Prime project.