ID 683283
Date 9/24/2018
Public

## 3.4.1.3. Synthesis Directives

The Intel® Quartus® Prime software supports synthesis directives, also commonly called compiler directives or pragmas. You can include synthesis directives in Verilog HDL or VHDL code as comments. These directives are not standard Verilog HDL or VHDL commands. Synthesis tools use directives to control the synthesis process. Directives do not apply to a specific design node, but change the behavior of the synthesis tool from the point in which they occur in the HDL source code. Other tools, such as simulators, ignore these directives and treat them as comments.

Table 15.  Specifying Synthesis DirectivesYou can enter synthesis directives in your code using the syntax in the following table, in which <directive> and <value> are variables, and the entry in brackets are optional. For synthesis directives, no equal sign before the value is necessary; this is different than the Verilog syntax for synthesis attributes. The examples demonstrate each syntax form.
Language Syntax Example
Verilog HDL4
// synthesis <directive> [ <value> ]
or
/* synthesis <directive> [ <value> ] */
VHDL
-- synthesis <directive> [ <value> ]
VHDL-2008
/* synthesis <directive> [<value>] */

In addition to the synthesis keyword shown above, the software supports the pragma, synopsys, and exemplar keywords in Verilog HDL and VHDL for compatibility with other synthesis tools. The Intel® Quartus® Prime software also supports the keyword altera, which allows you to add synthesis directives that only Intel® Quartus® Prime Integrated Synthesis feature recognizes, and not by other tools that recognize the same synthesis directives.

Note: Because formal verification tools ignore the exemplar, pragma, and altera keywords, Altera recommends that you avoid using these directive keywords when you use formal verification to prevent mismatches with the Intel® Quartus® Prime results.
4 Verilog HDL is case sensitive; therefore, all synthesis directives are also case sensitive.