Visible to Intel only — GUID: mwh1409959918467
Ixiasoft
Visible to Intel only — GUID: mwh1409959918467
Ixiasoft
3.5.8. Disabling Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute
Use the no_rw_check value for the ramstyle attribute, or disable the Add Pass-Through Logic to Inferred RAMs logic option assignment to indicate that your design does not depend on the behavior of the inferred RAM, when there are reads and writes to the same address in the same clock cycle. If you specify the attribute or disbale the logic option, the Intel® Quartus® Prime software chooses a read-during-write behavior instead of the read-during-write behavior of your HDL source code.
You disable or edit the attributes of this option by modifying the add_pass_through_logic_to_inferred_rams option in the Intel® Quartus® Prime Settings File (.qsf). There is no corresponding GUI setting for this option.
Sometimes, you must map an inferred RAM into regular logic cells because the inferred RAM has a read-during-write behavior that the TriMatrix memory blocks in your target device do not support. In other cases, the Intel® Quartus® Prime software must insert extra logic to mimic read-during-write behavior of the HDL source to increase the area of your design and potentially reduce its performance. In some of these cases, you can use the attribute to specify that the software can implement the RAM directly in a TriMatrix memory block without using logic. You can also use the attribute to prevent a warning message for dual-clock RAMs in the case that the inferred behavior in the device does not exactly match the read-during-write conditions described in the HDL code.
To set the Add Pass-Through Logic to Inferred RAMs logic option with the Intel® Quartus® Prime software, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).
These examples use two addresses and normally require extra logic after the RAM to ensure that the read-during-write conditions in the device match the HDL code. If your design does not require a defined read-during-write condition, the extra logic is not necessary. With the no_rw_check attribute, Intel® Quartus® Prime Integrated Synthesis does not generate the extra logic.
HDL | Code |
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Verilog HDL | |
VHDL | |
You can use a ramstyle attribute with the MLAB value, so that the Intel® Quartus® Prime software can infer a small RAM block and place it in an MLAB.
These examples show the method of setting two values to the ramstyle attribute with a small asynchronous RAM block, with the ramstyle synthesis attribute set, so that the software can implement the memory in the MLAB memory block and so that the read-during-write behavior is not important. Without the attribute, this design requires 512 registers and 240 ALUTs. With the attribute, the design requires eight memory ALUTs and only 15 registers.
HDL | Code |
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Verilog HDL | |
VHDL | |
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