- 188.8.131.52. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 184.108.40.206. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
1.9. Creating a Design Floorplan With LogicLock Regions
- To avoid resource conflicts between partitions, predominantly when partitions are imported from another Intel® Quartus® Prime project
- To ensure a good quality of results when recompiling individual timing-critical partitions
Design floorplan assignments prevent the situation in which the Fitter must place a partition in an area of the device where most resources are already used by other partitions. A physical region assignment provides a reasonable region to re-place logic after a change, so the Fitter does not have to scatter logic throughout the available space in the device.
Floorplan assignments are not required for non-critical partitions compiled as part of the top-level design. The logic for partitions that are not timing-critical (such as simple top-level glue logic) can be placed anywhere in the device on each recompilation, if that is best for your design.
The simplest way to create a floorplan for a partitioned design is to create one LogicLock region per partition (including the top-level partition). If you have a compilation result for a partitioned design with no LogicLock regions, you can use the Chip Planner with the Design Partition Planner to view the partition placement in the device floorplan. You can draw regions in the floorplan that match the general location and size of the logic in each partition. Or, initially, you can set each region with the default settings of Auto size and Floating location to allow the Intel® Quartus® Prime software to determine the preliminary size and location for the regions. Then, after compilation, use the Fitter-determined size and origin location as a starting point for your design floorplan. Check the quality of results obtained for your floorplan location assignments and make changes to the regions as needed. Alternatively, you can perform synthesis, and then set the regions to the required size based on resource estimates. In this case, use your knowledge of the connections between partitions to place the regions in the floorplan.
Once you have created an initial floorplan, you can refine the region using tools in the Intel® Quartus® Prime software. You can also use advanced techniques such as creating non‑rectangular regions by merging LogicLock regions.
You can use the Incremental Compilation Advisor to check that your LogicLock regions meet Altera’s guidelines.
Did you find the information on this page useful?