- 184.108.40.206. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 220.127.116.11. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
18.104.22.168. Creating LogicLock Regions
The floorplan-aware synthesis feature allows you to use LogicLock regions to define resource allocation for DSP blocks and RAM blocks. For example, if you assign a certain partition to a certain LogicLock region, resource balancing takes into account that all the DSP and RAM blocks in that partition need to fit in this LogicLock region. Resource balancing then balances the DSP and RAM blocks accordingly.
Because floorplan-aware balancing step considers only one partition at a time, it does not know that nodes from another partition may be using the same resources. When using this feature, Altera recommends that you do not manually assign nodes from different partitions to the same LogicLock region.
If you do not want the software to consider the LogicLock floorplan constraints when performing DSP and RAM balancing, you can turn off the floorplan-aware synthesis feature. Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) to disable Use LogicLock Constraints During Resource Balancing option.
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