- 184.108.40.206. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 220.127.116.11. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
18.104.22.168. Derived Clocks and PLLs in Design Partition Scripts
This issue is of particular importance for clock pins that require timing constraints and clock group settings. Problems can occur if your design uses logic or inversion to derive a new clock from a clock input pin. Make appropriate timing assignments in your lower-level Intel® Quartus® Prime project to ensure that clocks are not unconstrained.
If the lower-level design uses the top-level project framework from the project lead, the design will have all the required information about the clock and PLL settings. Otherwise, if you use a PLL in your top-level design and connect it to lower-level partitions, the lower-level partitions do not have information about the multiplication or phase shift factors in the PLL. Make appropriate timing assignments in your lower‑level Intel® Quartus® Prime project to ensure that clocks are not unconstrained or constrained with the incorrect frequency. Alternatively, you can manually duplicate the top‑level derived clock logic or PLL in the lower-level design file to ensure that you have the correct multiplication or phase-shift factors, compensation delays and other PLL parameters for complete and accurate timing analysis. Create a design partition for the rest of the lower-level design logic for export to the top level. When the lower‑level design is complete, export only the partition that contains the relevant logic.
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