Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

3.4.18. Noprune Synthesis Attribute/Preserve Fan-out Free Register Node

This synthesis attribute and corresponding logic option direct the Compiler to preserve a fan-out-free register through the entire compilation flow. This option is different from the Preserve Registers option, which prevents the Intel® Quartus® Prime software from reducing a register to a constant or merging with a duplicate register. Standard synthesis optimizations remove nodes that do not directly or indirectly feed a top-level output pin. This option can retain a register so you can observe the register in the Simulator or the Signal TapAdditionally, this option can retain registers if you create a preliminary version of your design in which you have not specified the fan-out logic of the register.

You can set the Preserve Fan-out Free Register Node logic option in the Intel® Quartus® Prime software, or you can set the noprune attribute in your HDL code, as shown in these examples. In these examples, the logic option or the attribute preserves the my_reg register.

Note: You must use the noprune attribute instead of the logic option if the register has no immediate fan-out in its module or entity. If you do not use the synthesis attribute, the software removes (or “prunes”) registers with no fan-out during Analysis & Elaboration before the logic synthesis stage applies any logic options. If the register has no fan-out in the full design, but has fan-out in its module or entity, you can use the logic option to retain the register through compilation.

The software supports the attribute name syn_noprune for compatibility with other synthesis tools.

Table 22.   Setting the noprune attribute in HDL code
HDL Code
Verilog HD
reg my_reg /* synthesis syn_noprune */;
Verilog-2001 and SystemVerilog
(* noprune *) reg my_reg;
signal my_reg : stdlogic;
attribute noprune: boolean;
attribute noprune of my_reg : signal is true;