- 18.104.22.168. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 22.214.171.124. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.18. Noprune Synthesis Attribute/Preserve Fan-out Free Register Node
This synthesis attribute and corresponding logic option direct the Compiler to preserve a fan-out-free register through the entire compilation flow. This option is different from the Preserve Registers option, which prevents the Intel® Quartus® Prime software from reducing a register to a constant or merging with a duplicate register. Standard synthesis optimizations remove nodes that do not directly or indirectly feed a top-level output pin. This option can retain a register so you can observe the register in the Simulator or the Signal TapAdditionally, this option can retain registers if you create a preliminary version of your design in which you have not specified the fan-out logic of the register.
You can set the Preserve Fan-out Free Register Node logic option in the Intel® Quartus® Prime software, or you can set the noprune attribute in your HDL code, as shown in these examples. In these examples, the logic option or the attribute preserves the my_reg register.
The software supports the attribute name syn_noprune for compatibility with other synthesis tools.
reg my_reg /* synthesis syn_noprune */;
|Verilog-2001 and SystemVerilog||
(* noprune *) reg my_reg;
signal my_reg : stdlogic; attribute noprune: boolean; attribute noprune of my_reg : signal is true;
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